1. Field of the Invention
This invention relates to the field of silicon on insulator (SOI) structures used in semiconductor devices and, in particular, to device isolation in SOI structures.
2. Background of the Invention
Silicon layers for silicon on insulator (SOI) structures have become thinner than that of previous generation SOI devices to reduce junction capacitance and to suppress history effects. Shallow trench isolation (STI) is one technique that has been used to electrically isolate devices on the SOI wafers. U.S. Pat. No. 6,599,813, the entire contents of which are incorporated herein by reference, describes the application of STI to SOI structures. As described therein, during conventional formation of shallow trenches on SOI structures, a typical STI formation process begins with formation of a pad oxide layer on top of the silicon layer of the SOI substrate, followed by deposition of a polish stop layer such as silicon nitride. Next, a trench is formed in the polish stop layer, the pad oxide layer, and the silicon layer of the SOI substrate, using conventional photolithography masking and etching techniques. A sidewall oxide may be thermally grown on the silicon sidewalls of the trench, to reduce the field emission effect. Then, the trench is filled with SiO2 by, for example, a high density plasma (HDP) deposition process. Excess SiO2 is removed by CMP (chemo-mechanical polishing) planarization down to the polish stop layer, and the polish stop layer is then removed.
The previously grown pad oxide layer, formed on top of the silicon layer of the SOI substrate, is removed by etching. During etching, some of the STI fill material also is inevitably removed. Next, a sacrificial oxide layer is grown on the silicon layer of the SOI structure. Well ion implants are then performed. Ion implantation of the SiO2 STI fill material is believed to cause the surface of the SiO2 to become very soft. Upon stripping of the sacrificial oxide layer, a significant amount of the softened SiO2 STI fill material may be removed, producing divots in the STI fill material. Portions of a gate oxide grown for device formation is later stripped, which leads to further etching of the STI material and formation of divots in the STI fill material.
STI fill material may also be inadvertently etched during cleaning steps. For example, an HF wet clean is needed for native oxide and/or metal contamination removal. The HF wet clean is an important step in the formation of subsequent layers to create interfaces between various components of the silicon transistor structures. For example, a cleaning step may be performed post gate etch, or prior to silicide formation. The silicon and the silicon oxide in the SOI structure, if exposed, must survive the HF wet cleans. Omission of the HF wet clean is not a viable option, as omission leads to various failures in the fabricated transistor devices, such as for example non-ohmic contact failure and/or high leakage current failure due to crystal defects. Thus, an SOI silicon thickness must accommodate the HF etching amount, which being unpredictable due to the nature of the native oxide formation limits the minimum thickness of the SOI silicon layer that must be provided.
One approach under consideration for thinner SOI layers is to use a raised source/drain (RSD) in which the source/drain regions of the transistor device on the SOI silicon layer are thicker (i.e., raised above the surface of the SOI silicon layer) than the channel layer in the transistor device. Trench isolations are then formed in between raised source drain regions of adjacent transistor devices. However, the conventional RSD technique still requires an HF cleaning step as a pre-clean prior to deposition of the silicon in the RSD regions. Accommodation of the additional HF step prior to the deposition of the silicon in the RSD regions means that the thickness of the SOI silicon layer to be utilized in the conventional RSD technique would be thicker than without RSD. Hence, even with the RSD technique, inadvertent etching of the silicon layer of the SOI structure occurs producing divots in the silicon layer.
Thus, removal of the STI fill material during the etching and cleaning steps, removal of the pad oxide exposing the silicon SOI layer, and removal of native oxides prior to RSD formation not only cause relatively large variations in STI material thickness, but also create divots in the silicon layer of the SOI structure. Further, in the progression to thinner SOI silicon layers, the present inventors have discovered that the divot depth has not become shallower because the divot depth is determined by the total amount of HF etching. As a result, the divot is expected in the near future to be deeper than the SOI silicon layer thickness.
Deep STI divots degrade not only threshold voltage variation for the transistors formed on the SOI silicon layer, but also affect manufacturing yield due to particle generation. For example, after the divot formation, the divot whether occurring in the STI fill material or in the silicon layer of the SOI layer, can be locally filled with a film such as SiN or photoresist in a deposition/etch process. The deposition/etch process, such as for example a spacer SiN deposition and a blanket reactive ion etching of the SiN, and/or photoresist coating and development can produce local film residue in the divot. Lift off of the local film residue in the divot by a wet etching process contributes to particles, reducing manufacturing yield.
Consequently, new device isolation methods are needed. Further, as the device dimensions become smaller, strong resolution enhancement technologies, such as for example alternating phase shift mask (PSM), have become necessary. Alternating phase shift masking is known in the art and described for example in U.S. Pat. No. 6,187,480 and U.S. Pat. No. 6,605,396, the entire contents of which are incorporated herein by reference. However, the auto shifter generator method involved in PSM is restricted by complicated layouts.